April 22, 2009
UCSB claims monolithic router world first
One of the most densely-integrated InP chips ever reported brings all-optical networks closer.
The 8-channel InP monolithic tunable optical router, or MOTOR, produced by University of California, Santa Barbara, scientists. The left half of the chip holds eight wavelength converter arrays, and the right holds the arrayed waveguide grating router. Credit: University of California, Santa Barbara.
Researchers at the University of California, Santa Barbara have made a key step towards eliminating optical-to-electrical-to-optical conversion stages in router hardware.
UCSB researchers Steve Nicholes and Milan Mašanović have produced the world's first eight-channel monolithic tunable optical router, operating error-free at 40 Gbit/s on a single InP/InGaAsP chip.
The 4.25 mm x 14.5 mm device integrates eight tunable wavelength converters with an arrayed waveguide grating router (AWGR). It contains over 200 functional elements, including more than 150 on-chip diodes, produced using 14 lithography steps.
The epitaxial structure includes ten compressively-strained quantum wells, and an undoped InP layer in the passive sections of the device that reduces absorption losses in its AWGR.
Nicholes and Mašanović produced the chip using a quantum well intermixing approach to broaden the bandgap of the quantum wells and define the passive regions. They then deposited p-type InP in a final regrowth step that buries the AWGR and defines the upper cladding of the device.
“We are able to use a structure with quantum wells sandwiched in the center of the waveguide to achieve high-gain semiconductor optical amplifiers and high-power sampled-grating distributed Bragg reflectors,” said project leader Daniel Blumenthal.
The team's ultimate goal is to shrink the size of state-of-the-art internet routers that occupy a full 7-foot equipment rack today down to a single linecard.
This requires pushing back the boundaries of how many optical devices can be integrated onto a single chip.
An eight-channel router is an impressive first step but Blumenthal already has his eye on 64-channel optical routers.
“The key is using 4-inch, and hopefully some day larger, InP or migrating to the new silicon/InP platforms that are coming out,” he told compoundsemiconductor.net.
“The larger wafers will be needed to get multiple devices this size, then of course the yield, ways to test and package, would all need to be worked out.”
The monolithic tunable optical router, or MOTOR, is a product of a project called LASOR that Blumenthal is principal investigator for.
Standing for “Label-switched optical router”, LASOR is in turn an approximately $18 million element of a US Department of Defense-funded project, called Data in Optical Domain-Network (DOD-N).
Sponsored by the DARPA Microsystems Technology Office and Army Research Labs, DOD-N aims to remove the need for any optical-to-electrical-to-optical conversions, and other communications system bottlenecks.
The LASOR project has been running since 2004 and is just finishing its Phase II work, with a 12-month duration Phase III stage already confirmed.
As reported in compoundsemiconductor.net